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Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process and Intel(R) Pentium(R) 4 Processor Extreme Edition Supporting Hyper-Threading Technology1
Datasheet 2 GHz - 3.40 GHz Frequencies Supporting Hyper-Threading Technology1 at 3.06 GHz with 533 MHz System Bus and All Frequencies with 800 MHz System Bus
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Available at 2 GHz, 2.20 GHz, 2.26 GHz, 2.40 GHz, 2.50 GHz, 2.53 GHz, 2.60 GHz, 2.66 GHz, 2.80 GHz, 3 GHz, 3.06 GHz, 3.20 GHz, and 3.40 GHz Supports Hyper-Threading Technology (HT Technology) at 3.06 GHz with 533 MHz system bus and all frequencies with 800 MHz system bus Binary compatible with applications running on previous members of the Intel microprocessor line Intel NetBurst(R) microarchitecture System bus frequency at 400 MHz, 533 MHz, and 800 MHz Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency Hyper-Pipelined Technology -- Advance Dynamic Execution -- Very deep out-of-order execution Enhanced branch prediction Optimized for 32-bit applications running on advanced 32-bit operating systems
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8-KB Level 1 data cache Level 1 Execution Trace Cache stores 12-K micro-ops and removes decoder latency from main execution loops 512-KB Advanced Transfer Cache (on-die, full-speed Level 2 (L2) cache) with 8-way associativity and Error Correcting Code (ECC) 2-MB Integrated Level 3 (L3) cache with 8-way associativity that is supported by Intel(R) Pentium(R) 4 Processor Extreme Edition Supporting Hyper-Threading Technology 144 Streaming SIMD Extensions 2 (SSE2) instructions Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance Power Management capabilities -- System Management mode -- Multiple low-power states 8-way cache associativity provides improved cache hit rate on load/store operations 478-Pin Package
The Intel(R) Pentium(R) 4 processor family supporting Hyper-Threading Technology1 (HT Technology) delivers Intel's most advanced, most powerful processors for desktop PCs and entry-level workstations, which are based on the Intel NetBurst(R) microarchitecture. The Pentium 4 processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments. The Intel(R) Pentium(R) 4 processor Extreme Edition supporting HT Technology features 2 MB of L3 cache and offers high levels of performance targeted specifically for high-end gamers and computing power users.
February 2004 Document Number: 298643-012
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel(R) Pentium(R) 4 processor on 0.13 micron process may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
1 Hyper-Threading Technology requires a computer system with an Intel(R) Pentium(R) 4 processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See <> for more information including details on which processors support HT Technology.
Intel, Pentium, Intel NetBurst, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2001-2004, Intel Corporation
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Contents
1 Introduction .................................................................................................................. 9
1.1 1.2 Terminology.........................................................................................................11 1.1.1 Processor Packaging Terminology.........................................................11 References ..........................................................................................................12 System Bus and GTLREF ...................................................................................15 Power and Ground Pins ......................................................................................15 Decoupling Guidelines ........................................................................................16 2.3.1 VCC Decoupling .....................................................................................16 2.3.2 System Bus AGTL+ Decoupling.............................................................16 Voltage Identification ...........................................................................................16 2.4.1 Phase Lock Loop (PLL) Power and Filter...............................................18 Reserved, Unused Pins, and TESTHI[12:0]........................................................20 System Bus Signal Groups .................................................................................21 Asynchronous GTL+ Signals...............................................................................22 Test Access Port (TAP) Connection....................................................................22 System Bus Frequency Select Signals (BSEL[1:0])............................................22 Maximum Ratings................................................................................................23 Processor DC Specifications...............................................................................23 AGTL+ System Bus Specifications .....................................................................35 Package Load Specifications ..............................................................................40 Processor Insertion Specifications ......................................................................41 Processor Mass Specifications ...........................................................................41 Processor Materials.............................................................................................41 Processor Markings.............................................................................................42 Processor Pin Assignments ................................................................................45 Signal Descriptions..............................................................................................58 Processor Thermal Specifications.......................................................................68 5.1.1 Thermal Specifications ...........................................................................68 5.1.2 Thermal Metrology .................................................................................70 5.1.2.1 Processor Case Temperature Measurement ............................70 Power-On Configuration Options ........................................................................71 Clock Control and Low Power States..................................................................71 6.2.1 Normal State--State 1 ...........................................................................71 6.2.2 AutoHALT Powerdown State--State 2...................................................72 6.2.3 Stop-Grant State--State 3 .....................................................................73 6.2.4 HALT/Grant Snoop State--State 4 ........................................................73 6.2.5 Sleep State--State 5..............................................................................74
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Electrical Specifications........................................................................................15
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12
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Package Mechanical Specifications.................................................................37
3.1 3.2 3.3 3.4 3.5
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Pin Lists and Signal Descriptions.....................................................................45
4.1 4.2
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Thermal Specifications and Design Considerations .................................67
5.1
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Features .......................................................................................................................71
6.1 6.2
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6.3
Thermal Monitor .................................................................................................. 74 6.3.1 Thermal Diode........................................................................................ 76 Introduction ......................................................................................................... 77 Mechanical Specifications................................................................................... 78 7.2.1 Boxed Processor Cooling Solution Dimensions ..................................... 78 7.2.2 Boxed Processor Fan Heatsink Weight.................................................. 79 7.2.3 Boxed Processor Retention Mechanism and Heatsink Assembly.......... 79 Electrical Requirements ...................................................................................... 80 7.3.1 Fan Heatsink Power Supply ................................................................... 80 Thermal Specifications........................................................................................ 82 7.4.1 Boxed Processor Cooling Requirements ............................................... 82 7.4.2 Variable Speed Fan ............................................................................... 83 Logic Analyzer Interface (LAI)............................................................................. 85 8.1.1 Mechanical Considerations .................................................................... 85 8.1.2 Electrical Considerations........................................................................ 85
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Boxed Processor Specifications ....................................................................... 77
7.1 7.2
7.3 7.4
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Debug Tools Specifications................................................................................. 85
8.1
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Figures
2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 5-1 5-2 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 VCCVID Pin Voltage and Current Requirements .................................................17 Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................19 Phase Lock Loop (PLL) Filter Requirements ......................................................19 VCC Static and Transient Tolerance (For Intel(R) Pentium(R) 4 Processor With 512-KB L2 Cache on 0.13 Micron Process)...............................29 VCC Static and Transient Tolerance (For Intel(R) Pentium(R) 4 Processor Extreme Edition Supporting Hyper-Threading Technology)...............31 ITPCLKOUT[1:0] Output Buffer Diagram ............................................................34 Test Circuit ..........................................................................................................35 Exploded View of Processor Components on a System Board ..........................37 Processor Package .............................................................................................38 Processor Cross-Section and Keep-In ................................................................39 Processor Pin Detail............................................................................................39 IHS Flatness Specification ..................................................................................40 Processor Markings (Processors with Fixed VID) ...............................................42 Processor Markings (Processors with Multiple VID) ...........................................42 The Coordinates of the Processor Pins As Viewed from the Top of the Package ....................................................................................................43 Example Thermal Solution (Not to Scale) ...........................................................67 Guideline Locations for Case Temperature (TC) Thermocouple Placement ......70 Stop Clock State Machine ...................................................................................72 Mechanical Representation of the Boxed Processor ..........................................77 Side View Space Requirements for the Boxed Processor ..................................78 Top View Space Requirements for the Boxed Processor ...................................79 Boxed Processor Fan Heatsink Power Cable Connector Description.................80 MotherBoard Power Header Placement Relative to Processor Socket ..............81 Boxed Processor Fan Heatsink Airspace Keep-Out Requirements (Side 1 View) .......................................................................................................82 Boxed Processor Fan Heatsink Airspace Keep-Out Requirements (Side 2 View) .......................................................................................................83 Boxed Processor Fan Heatsink Set Points .........................................................83
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Tables
1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 3-1 3-2 3-3 3-4 4-1 4-2 4-3 5-1 6-1 6-2 6-3 7-1 7-2 References.......................................................................................................... 12 VCCVID Pin Voltage Requirements ..................................................................... 17 Voltage Identification Definition........................................................................... 18 System Bus Pin Groups ...................................................................................... 21 BSEL[1:0] Frequency Table for BCLK[1:0] ......................................................... 22 Processor DC Absolute Maximum Ratings ......................................................... 23 Voltage and Current Specifications..................................................................... 24 VCC Static and Transient Tolerance (For Intel(R) Pentium(R) 4 Processor With 512-KB L2 Cache on 0.13 Micron Process) .............................. 28 Vcc Static and Transient Tolerance (For Intel(R) Pentium(R) 4 Processor Extreme Edition Supporting Hyper-Threading Technology) .............. 30 AGTL+ Signal Group DC Specifications ............................................................. 32 Asynchronous GTL+ Signal Group DC Specifications ........................................ 32 PWRGOOD and TAP Signal Group DC Specifications ...................................... 33 ITPCLKOUT[1:0] DC Specifications.................................................................... 33 BSEL [1:0] and VID[4:0] DC Specifications......................................................... 34 AGTL+ Bus Voltage Definitions........................................................................... 35 Description Table for Processor Dimensions ...................................................... 38 Package Dynamic and Static Load Specifications .............................................. 40 Processor Mass .................................................................................................. 41 Processor Material Properties............................................................................. 41 Pin Listing by Pin Name ...................................................................................... 46 Pin Listing by Pin Number................................................................................... 52 Signal Descriptions ............................................................................................. 58 Processor Thermal Design Power ...................................................................... 69 Power-On Configuration Option Pins .................................................................. 71 Thermal Diode Parameters ................................................................................. 76 Thermal Diode Interface...................................................................................... 76 Fan Heatsink Power and Signal Specifications................................................... 81 Boxed Processor Fan Heatsink Set Points ......................................................... 84
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Revision History
Revision -005 Description Added Thermal and Electrical Specifications for frequencies through 3.06 GHz and included multiple VID specifications. Updated the THERMTRIP# and DBI# signal descriptions. Removed Deep Sleep State section. Updated Boxed Processor Fan Heatsink Set Points table and figure. Update Poweron Configuration Option pins table. Minor update to DC specifications Corrected Table 4-3, Signal Description. Item TRST#, last sentence. Measurement changed from 680 W pull-down resistor to 680 pull-down resistor. Added 800 MHz system bus specifications. Added IMPSEL definition. Updated Stop-Grant, HALT, and AutoHALT states Added thermal and electrical specifications for 2.40C GHz, 2.60C GHz, and 2.80C GHz with 800 MHz system bus. Updated thermal specifications and thermal monitor chapter. Updated PROCHOT# pin definition. Added thermal and electrical specifications for 3.20C GHz. Updated processor markings. Added Intel(R) Pentium(R) 4 Processor Extreme Edition Supporting HyperThreading Technology Added 3.40 GHz thermal and electrical specifications for the Intel Pentium 4 Processor Extreme Edition and Intel Pentium 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Date November 2002
-006 -007
December 2002 January 2003
-008 -009
April 2003 May 2003
-010 -011 -012
June 2003 November 2003 February 2004
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Introduction
Introduction
1
The Intel(R) Pentium(R) 4 processor with 512-KB L2 cache on 0.13 micron process and the Intel(R) Pentium(R) 4 processor Extreme Edition supporting Hyper-Threading Technology are follow-on processors to the Intel(R) Pentium(R) 4 processor in the 478-pin package with Intel NetBurst(R) microarchitecture. These processors use Flip-Chip Pin Grid Array (FC-PGA2) package technology, and plug into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Pentium 4 processor with 512-KB L2 cache on 0.13 micron process and the Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology, like the Pentium 4 processor in the 478-pin package, are based on the same Intel 32-bit microarchitecture and maintain the tradition of compatibility with IA-32 software. The Pentium 4 processor with 512-KB L2 cache on 0.13 micron process contains an on-die 512-KB advanced transfer L2 cache. The Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology contains an on-die 512-KB level 2 (L2) advanced transfer cache and an on-die 2-MB integrated level 3 (L3) cache. Both processors are on a 0.13 micron process. This document covers the Pentium 4 processors with 512-KB L2 cache on 0.13 micron process and the Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology. Note: Unless otherwise specified in this document, the term "Pentium 4 processor on 0.13 micron process" (or simply processor) refers to both the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process and the Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology. Hyper-Threading Technology1 is a new feature in the Pentium 4 processor on 0.13 micron process at 800 MHz system bus. It is also on the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process at 3.06 GHz/533 MHz system bus. HT Technology allows a single, physical Pentium 4 processor on 0.13 micron process to function as two logical processors. While some execution resources (such as caches, execution units, and buses) are shared, each logical processor has its own architecture state with its own set of general-purpose registers, control registers to provide increased system responsiveness in multitasking environments, and headroom for next generation multi-threaded applications. Intel recommends enabling HT Technology with Microsoft Windows* XP Professional or Windows* XP Home, and disabling HT Technology via the BIOS for all previous versions of Windows operating systems. For more information on HyperThreading Technology, see www.intel.com/info/hyperthreading. Refer to Section 6.1 for HT Technology configuration details. The Intel NetBurst microarchitecture features include hyper-pipelined technology, a rapid execution engine, a 400 MHz, 533 MHz, or 800 MHz system bus, and an execution trace cache. The hyper-pipelined technology doubles the pipeline depth in the Pentium 4 processor on 0.13 micron process, allowing the processor to reach much higher core frequencies. The rapid execution engine allows the two integer ALUs in the processor to run at twice the core frequency; this allows many integer instructions to execute in 1/2 clock cycle. The 400 MHz, 533 MHz, or 800 MHz system bus is a quad-pumped bus running off a 100 MHz or a 133 MHz system clock, making 3.2 Gbytes/sec, 4.3 Gbytes/sec, or 6.4 Gbytes/sec data transfer rates possible. The execution trace cache is a first-level cache that stores approximately 12-K decoded microoperations that removes the instruction decoding logic from the main execution path, thereby increasing performance.
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Introduction
Additional features within the Intel NetBurst microarchitecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the processor. The advanced transfer cache is a 512-KB, on-die level 2 (L2) cache. A new floating point and multi-media unit has been implemented that provides superior performance for multi-media and mathematically intensive applications. Finally, SSE2 adds 144 new instructions for double-precision floating point, SIMD integer, and memory management. Power management capabilities (such as AutoHALT, Stop-Grant, and Sleep) have been retained. The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques (such as ray tracing). The 2-MB L3 cache is available with only the Pentium 4 processor Extreme Edition. The additional third level of cache is located on the processor die and is designed specifically to meet the compute needs of high-end gamers and other power users. The integrated level 3 cache is available in 2-MB and is coupled with the 800 MHz system bus to provide a high bandwidth path to memory. The efficient design of the integrated Level 3 cache provides a faster path to large data sets stored in cache on the processor. This results in reduced average memory latency and increased throughput for larger workloads. The Intel NetBurst microarchitecture system bus on the Pentium 4 processor on 0.13 micron process uses a split-transaction, deferred reply protocol like the Pentium 4 processor in the 478-pin package. This system bus is not compatible with the P6 processor family bus. The Intel NetBurst microarchitecture system bus uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 6.4 Gbytes/second. Intel will enable support components for the Pentium 4 processor on 0.13 micron process including heatsinks, heatsink retention mechanisms, and sockets. Manufacturability is a high priority; hence, mechanical assembly can be completed from the top of the motherboard, and should not require any special tooling. The processor system bus uses a variant of GTL+ signalling technology called Assisted Gunning Transceiver Logic (AGTL+) signal technology.
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Introduction
1.1
Terminology
A `#' symbol after a signal name refers to an active low signal, indicating that the signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the `#' symbol indicates that the signal is inverted. For example, D[3:0] = `HLHL' refers to a hex `A', and D[3:0]# = `LHLH' also refers to a hex `A' (H= High logic level, L= Low logic level). The term "System Bus" refers to the interface between the processor and system core logic (also known as the chipset components). The system bus is a multiprocessing interface to processors, memory, and I/O.
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification: * Intel Pentium 4 processor in the 478-pin package -- 0.18-micron Pentium 4 processor core in the FC-PGA2 package. * Intel Pentium 4 processor in the 423-pin package -- 0.18-micron Pentium 4 processor core in the PGA package. * Intel Pentium 4 processor with 512-KB L2 cache on 0.13 micron process -- 0.13 micron version of Pentium 4 processor in the 478-pin package core in the FC-PGA2 package with a 512-KB L2 cache. * Intel Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology -- 0.13 micron version of Pentium 4 processor in the 478-pin package core in the FC-PGA2 package with a 512-KB L2 cache and a 2-MB L3 cache. * Processor -- For this document, the term processor shall mean Pentium 4 processor with 512-KB L2 cache on 0.13 micron process and the Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology. * Keep-out zone -- The area on or near the processor that system design can not utilize. This area must be kept free of all components to make room for the processor package, retention mechanism, heatsink, and heatsink clips. * Hyper-Threading Technology -- Hyper-Threading Technology allows a single, physical Pentium 4 processor to function as two logical processors when the necessary system ingredients are present. For more information, see: www.intel.com/info/hyperthreading. * Intel 875P chipset -- Chipset that supports DDR memory technology for the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process. This chipset also supports the Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology in platforms that meet the thermal design guidelines for this processor. * Intel 865G/865GV/865PE chipset -- Chipset that supports DDR memory technology for the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process. * Intel 865P chipset -- Chipset that supports DDR memory technology for the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process. * Intel 850 chipset -- Chipset that supports Rambus RDRAM* memory technology for Pentium 4 processor with 512-KB L2 cache on 0.13 micron process and Pentium 4 processor in the 478-pin package. * Intel 845 chipset -- Chipset that supports PC133 and DDR memory technologies for the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process and Pentium 4 processor in the 478-pin package.
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Introduction
* Processor core -- Pentium 4 processor with 512-KB L2 cache on 0.13 micron process core * * * *
die with integrated L2 cache and the Pentium 4 processor Extreme Edition supporting HyperThreading Technology core die with integrated L2 and L3 caches. FC-PGA2 package -- Flip-Chip Pin Grid Array package with 50-mil pin pitch and integrated heat spreader. mPGA478B socket -- Surface mount, 478 pin, Zero Insertion Force (ZIF) socket with 50-mil pin pitch. The socket mates the processor to the system board. Integrated heat spreader -- The surface used to make contact between a heatsink or other thermal solution and the processor. Integrated heat spreader is abbreviated IHS. Retention mechanism -- The structure mounted on the system board that provides support and retention of the processor heatsink.
1.2
References
Material and concepts available in the following documents may be beneficial when reading this document.
Table 1-1. References (Sheet 1 of 2)
Document Intel(R) 875P Chipset Platform Design Guide Intel(R) 865G/865PE/865P Chipset Platform Design Guide Intel(R) Pentium(R) 4 Processor in the 478-Pin Package / Intel(R) 850 Chipset Platform Family Design Guide Intel(R) Pentium(R) 4 Processor in the 478-Pin Package and Intel(R) 845 Chipset Platform for DDR Platform Design Guide Intel(R) Pentium(R) 4 Processor in the 478-Pin Package and Intel(R) 845E Chipset Platform for DDR Platform Design Guide Intel(R) Pentium(R) 4 Processor in the 478-Pin Package and Intel(R) 845 Chipset Platform for SDR Platform Design Guide Intel(R) Pentium(R) 4 Processor in the 478-Pin Package and Intel(R) 845GE/845PE Chipset Platform Design Guide Intel(R) Pentium(R) 4 Processor in 478-pin Package and Intel(R) 845G/845GL/845GV Chipset Platform Design Guide Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines Mechanical Enabling for the Intel(R) Pentium(R) 4 Processor in the 478-pin Package Assembling Intel Reference Components for the Intel(R) Pentium(R) 4 Processor in the 478-pin Package Voltage Regulator-Down (VRD) 10.0: for Desktop Socket 478 Design Guide Voltage Regulator Module (VRM) 9.0 DC-DC Converter Design Guidelines Intel(R) Pentium(R) 4 Processor VR-Down Design Guidelines CK00 Clock Synthesizer/Driver Design Guidelines Intel(R) Pentium(R)4 Processor 478-Pin Socket (mPGA478B) Socket Design Guidelines Location http://developer.intel.com/design/ chipsets/designex/252527.htm http://developer.intel.com/design/ chipsets/designex/252518.htm http://developer.intel.com/design/ pentium4/guides/249888.htm http://developer.intel.com/design/ chipsets/designex/298605.htm http://developer.intel.com/design/ chipsets/designex/298652.htm http://developer.intel.com/design/ chipsets/designex/298354.htm http://developer.intel.com/design/ chipsets/designex/251925.htm http://developer.intel.com/design/ chipsets/designex/298654.htm http://developer.intel.com/design/ pentium4/guides/252161.htm http://developer.intel.com/design/ pentium4/guides/290728.htm http://developer.intel.com/design/ pentium4/guides/298590.htm http://developer.intel.com/design/ pentium4/guides/252885.htm http://developer.intel.com/design/ pentium4/guides/249205.htm http://developer.intel.com/design/ Pentium4/guides/249891.htm http://developer.intel.com/design/ pentium4/guides/249206.htm http://developer.intel.com/design/ pentium4/guides/249890.htm
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Introduction
Table 1-1. References (Sheet 2 of 2)
Document IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture IA-32 Intel(R) Architecture Software Developer's Manual, Volume 2: Instruction Set Reference IA-32 Intel(R) Architecture Software Developer's Manual, Volume 3: System Programming Guide AP-485 Intel(R) Processor Identification and the CPUID Instruction ITP700 Debug Port Design Guide
(R)
Location http://developer.intel.com/design/ pentium4/manuals/245470.htm http://developer.intel.com/design/ pentium4/manuals/245471.htm http://developer.intel.com/design/ pentium4/manuals/245472.htm http://developer.intel.com/design/ xeon/applnots/241618.htm http://developer.intel.com/design/ Xeon/guides/249679.htm
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Introduction
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Electrical Specifications
Electrical Specifications
2.1 System Bus and GTLREF
2
Most Pentium 4 processor on 0.13 micron process system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the P6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Like the Pentium 4 processor in the 478-pin package, the termination voltage level for the Pentium 4 processor on 0.13 micron process AGTL+ signals is VCC, which is the operating voltage of the processor core. The use of a termination voltage that is determined by the processor core allows better voltage scaling on the system bus for the Pentium 4 processor on 0.13 micron process. Because of the speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. Design guidelines for the Pentium 4 processor on 0.13 micron process system bus are detailed in the appropriate platform design guide (refer to Table 1-1). The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. Termination resistors are provided on the processor silicon and are terminated to its core voltage (VCC). The Intel(R) 875P chipset, Intel(R) 865G/865GV/865PE/865P chipsets, Intel(R) 850 chipset, and the Intel(R) 845 chipset also provide on-die termination. This eliminates the need to terminate the bus on the system board for most AGTL+ signals. However, some AGTL+ signals do not include on-die termination and must be terminated on the system board. For more information, refer to the appropriate platform design guide. The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system. For more information, refer to the appropriate platform design guide.
2.2
Power and Ground Pins
For clean on-chip power distribution, the Pentium 4 processor on 0.13 micron process has 85 VCC (power) and 180 VSS (ground) inputs. All power pins must be connected to VCC, while all VSS pins must be connected to a system ground plane.The processor VCC pins must be supplied with the voltage defined by the VID (Voltage ID) pins and the loadline specifications (see Figure 2-4).
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Electrical Specifications
2.3
Decoupling Guidelines
Because of the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2-6. Failure to do so can result in timing violations and/or affect the long term reliability of the processor. For further information and design guidelines, refer to the appropriate platform design guide and the Intel(R) Pentium(R) 4 Processor VR-Down Design Guidelines.
2.3.1
VCC Decoupling
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by bus and processor activity. Consult the Voltage Regulator Down design guide and appropriate platform design guide for further information.
2.3.2
System Bus AGTL+ Decoupling
Pentium 4 processors on 0.13 micron process integrate signal termination on the die and incorporate high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation. For more information, refer to the appropriate platform design guide.
2.4
Voltage Identification
The VID specification for Pentium 4 processors on 0.13 micron process is supported by the Intel(R) Pentium(R) 4 Processor VR-Down Design Guidelines, Voltage Regulator-Down (VRD) 10.0 Design Guide, and Voltage Regulator-Down (VRD) 10.0 Design Guide Addendum. The voltage set by the VID pins is the maximum voltage allowed by the processor. A minimum voltage is provided in Table 2-6 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification. The specifications have been set such that one voltage regulator can work with all supported frequencies. Pentium 4 processors on 0.13 micron process use five voltage identification pins, VID[4:0], to support automatic selection of power supply voltages. The VID pins for the Pentium 4 processor on 0.13 micron process are open drain outputs driven by the processor VID circuitry. The VID signals rely on pull-up resistors tied to a 3.3 V (maximum) supply to set the signal to a logic high level. These pull-up resistors may be either external logic on the motherboard, or internal to the Voltage Regulator. Table 2-2 specifies the voltage level corresponding to the state of VID[4:0]. A `1' in this table refers to a high voltage level, and a `0' refers to low voltage level. The definition provided in Table 2-2 is not related in any way to previous P6 processors or VRs, but is compatible with the Pentium 4 processor in the 478-pin package. If the processor socket is empty (VID[4:0] = 11111) or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. See the Intel(R) Pentium(R) 4 Processor VR-Down Design Guidelines, Voltage Regulator-Down (VRD) 10.0 Design Guide, or Voltage Regulator-Down (VRD) 10.0 Design Guide Addendum for more details.
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Power source characteristics must be stable when the supply to the voltage regulator is stable. Refer to the appropriate platform design guide for timing details of the power up sequence. Refer to the appropriate platform design guide for implementation details. The Voltage Identification circuit requires an independent 1.2 V supply. This voltage must be routed to the processor VCCVID pin. Figure 2-1 and Table 2-1 show the voltage and current requirements of the VCCVID pin. Table 2-1. VCCVID Pin Voltage Requirements
Symbol VCCVID Parameter VCC for Voltage Identification circuit Min -5% Typ 1.2 Max +10% Unit V 1 Notes
NOTE: 1. This specification applies to both static and transient components. The rising edge of VCCVID must be monotonic from 0 to 1.1 V. See Figure 2-1 for current requirements. In this case, monotonic is defined as continuously increasing with less than 50 mV of peak to peak noise for any width greater than 2 ns superimposed on the rising edge.
Figure 2-1. VCCVID Pin Voltage and Current Requirements
1.2 V + 10% 1.2 V - 5% 1.0 V VCCVID 30 mA 1 mA 4 ns VIDs latched
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Electrical Specifications
Table 2-2. Voltage Identification Definition
Processor Pins VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VCC_MAX VRM output off 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600
2.4.1
Phase Lock Loop (PLL) Power and Filter
VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Pentium 4 processor on 0.13 micron process. Since these PLLs are analog, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system; it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC. A typical filter topology is shown in Figure 2-2. The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or CIO in Figure 2-2), is as follows:
* * * *
< 0.2 dB gain in pass band < 0.5 dB attenuation in pass band < 1 Hz > 34 dB attenuation from 1 MHz to 66 MHz > 28 dB attenuation from 66 MHz to core frequency
Refer to the appropriate platform design guide for recommendations on implementing the filter.
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Electrical Specifications
Figure 2-2. Typical VCCIOPLL, VCCA and VSSA Power Distribution
VCC L VCCA CA VSSA CIO L
.
PLL Processor Core
VCCIOPLL
Figure 2-3. Phase Lock Loop (PLL) Filter Requirements
0.2 dB 0 dB -0.5 dB Forbidden Zone
Forbidden Zone -28 dB
-34 dB
DC
1 Hz Passband
fpeak
1 MHz
66 MHz High Frequency Band
fcore
NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Electrical Specifications
2.5
Reserved, Unused Pins, and TESTHI[12:0]
All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Pentium 4 processors on 0.13 micron process. See Chapter 4 for a pin listing of the processor and the location of all RESERVED pins. For reliable operation, always connect unused inputs or bidirectional signals that are not terminated on the die to an appropriate signal level. Note that on-die termination has been included on the Pentium 4 processor on 0.13 micron process to allow signals to be terminated within the processor silicon. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Table 2-3 lists details on AGTL+ signals that do not include ondie termination. Unused active high inputs should be connected through a resistor to ground (VSS). Refer to the appropriate platform design guide for the appropriate resistor values. Unused outputs can be left unconnected. However, this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For unused AGTL+ input or I/O signals that don't have on-die termination, use pull-up resistors of the same value in place of the on-die termination resistors (RTT). See Table 2-14. The TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Inputs and used outputs must be terminated on the system board. Unused outputs may be terminated on the system board or left unconnected. Note that leaving unused output unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. Signal termination for these signal types is discussed in the appropriate platform design guide listed in Table 1-1. The TESTHI pins should be tied to the processor VCC using a matched resistor, where a matched resistor has a resistance value within 20% of the impedance of the board transmission line traces. For example, if the trace impedance is 50 , then a value between 40 and 60 is required. The TESTHI pins may use individual pull-up resistors or may be grouped together as follows: 1. 2. 3. 4. TESTHI[1:0] TESTHI[5:2] TESTHI[10:8] TESTHI[12:11]
A matched resistor should be used for each group. Additionally, if the ITPCLKOUT[1:0] pins are not used, they may be connected individually to VCC using matched resistors or may be grouped with TESTHI[5:2] with a single matched resistor. If they are being used, individual termination with 1 k resistors is required. Tying ITPCLKOUT[1:0] directly to VCC or sharing a pull-up resistor to VCC will prevent use of debug interposers. This implementation is strongly discouraged for system boards that do not implement an inboard debug port. As an alternative, group2 (TESTHI[5:2]) and the ITPCLKOUT[1:0] pins may be tied directly to the processor VCC. This has no impact on system functionality. TESTHI0 and TESTHI12 may also be tied directly to the processor VCC if resistor termination is a problem, but matched resistor termination is recommended. In the case of the ITPCLKOUT[1:0] pins, direct tie to VCC is strongly discouraged for system boards that do not implement an inboard debug port. Tying any of the TESTHI pins together will prevent the ability to perform boundary scan testing.
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Electrical Specifications
2.6
System Bus Signal Groups
To simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals that are dependent on the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.), and the second set is for the source synchronous signals that are relative to their respective strobe lines (data and address), as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 2-3 identifies which signals are common clock, source synchronous, and asynchronous signals.
Table 2-3. System Bus Pin Groups
Signal Group AGTL+ Common Clock Input AGTL+ Common Clock I/O Type Common Clock Synchronous Signals1 BPRI#, DEFER#, RESET#2, RS[2:0]#, RSP#, TRDY# AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR# Signals REQ[4:0]#, A[16:3]#5 A[35:17]#5 D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
AGTL+ Source Synchronous I/O
Source Synchronous
AGTL+ Strobes Asynchronous GTL+ Input4,5 Asynchronous GTL+ Output4 Asynchronous GTL+ Input/ Output4 TAP Input4 TAP Output4 System Bus Clock Power/Other
Common Clock Asynchronous Asynchronous Asynchronous Synchronous to TCK Synchronous to TCK N/A N/A
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, STPCLK# FERR#, IERR#2, THERMTRIP# PROCHOT# TCK, TDI, TMS, TRST# TDO BCLK[1:0], ITP_CLK[1:0]3 VCC, VCCA, VCCIOPLL, VCCVID, VID[4:0], VSS, VSSA, GTLREF[3:0], COMP[1:0], RESERVED, TESTHI[5:0, 12:8], ITPCLKOUT[1:0], THERMDA, THERMDC, IMPSEL, DBR#3, PWRGOOD, SKTOCC#, VCC_SENSE, VSS_SENSE, BSEL[1:0],
NOTES: 1. Refer to Section 5.2 for signal descriptions. 2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 and the ITP700 Debug Port Design Guide for termination requirements. 3. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 4. These signal groups are not terminated by the processor. Refer to Section 2.5, the ITP700 Debug Port Design Guide, and the appropriate Platform Design Guide for termination requirements and further details. 5. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details.
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Electrical Specifications
2.7
Asynchronous GTL+ Signals
The Pentium 4 processor on 0.13 micron process does not use CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals (such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and STPCLK#) use GTL+ input buffers. Legacy output FERR# and other non-AGTL+ signals (THERMTRIP#) use GTL+ output buffers. PROCHOT# uses GTL+ input/output buffer. All of these signals follow the same DC requirements as AGTL+ signals; however, the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major difference between GTL+ and AGTL+). These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the Asynchronous GTL+ signals are required to be asserted for at least two BCLKs for the processor to recognize them. See Section 2.11 for the DC specifications for the Asynchronous GTL+ signal groups. See Section 6.2 for additional timing requirements for entering and leaving the low power states.
2.8
Test Access Port (TAP) Connection
Because of the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Pentium 4 processor on 0.13 micron process be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be required, with each driving a different voltage level.
2.9
System Bus Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] are output signals used to select the frequency of the processor input clock (BCLK[1:0]). Table 2-4 defines the possible combinations of the signals, and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Pentium 4 processor with 512-KB L2 cache on 0.13 micron process currently operates at a 400 MHz, 533 MHz, or 800 MHz system bus frequency. The Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology currently operates at 800 MHz system bus frequency. Individual processors will operate only at their specified system bus frequency. For more information about these pins, refer to Section 4.2 and the appropriate platform design guidelines.
Table 2-4. BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1 L L H H BSEL0 L H L H Function 100 MHz 133 MHz 200 MHz RESERVED
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Electrical Specifications
2.10
Maximum Ratings
Table 2-5 lists the processor's maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from Electro Static Discharge (ESD), one should always take precautions to avoid high static voltages or electric fields.
Table 2-5. Processor DC Absolute Maximum Ratings
Symbol TSTORAGE VCC VinAGTL+ VinAsynch_GTL+ IVID Parameter Processor storage temperature Any processor supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS Asynch GTL+ buffer DC input voltage with respect to VSS Max VID pin current Min -40 -0.3 -0.1 -0.1 Max 85 1.75 1.75 1.75 5 Unit C V V V mA Notes 2 1
NOTES: 1. This rating applies to any processor pin. 2. Contact Intel for storage requirements in excess of one year.
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core silicon unless noted otherwise. See Chapter 4 for the pin signal definitions and signal pin assignments. Most of the signals on the processor system bus are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 2-9. Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The DC specifications for these signal groups are listed in Table 2-10. Table 2-6 through Table 2-10 list the DC specifications for the Pentium 4 processor on 0.13 micron process, and are valid only while meeting specifications for case temperature, clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter. Processors with multiple VID have ICC_MAX of the highest VID for the specified frequency. For example, for processors through 2.80 GHz, the ICC_MAX would be the one at VID=1.525 V.
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Electrical Specifications
Table 2-6. Voltage and Current Specifications (Sheet 1 of 4)
Symbol Parameter VCC for Processor at VID=1.475 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz VCC (400 MHz FSB) VCC for Processor at VID=1.500 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz VCC for Processor at VID=1.525 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz VCC for Processor at VID=1.475 V 2.26 GHz 2.40B GHz 2.53 GHz 2.66 GHz 2.80 GHz 3.06 GHz VCC for Processor at VID=1.500 V VCC (533 MHz FSB) 2.26 GHz 2.40B GHz 2.53 GHz 2.66 GHz 2.80 GHz 3.06 GHz VCC for Processor at VID=1.525 V 2.26 GHz 2.40B GHz 2.53 GHz 2.66 GHz 2.80 GHz 3.06 GHz VCC for Processor at VID=1.550 V 3.06 GHz 1.340 1.425 1.355 1.350 1.345 1.345 1.340 1.315 1.435 1.430 1.430 1.420 1.420 1.395 1.330 1.330 1.325 1.320 1.315 1.290 Refer to Table 2-7 and Figure 2-4 1.405 1.405 1.400 1.395 1.395 1.370 1.305 1.300 1.295 1.295 1.290 1.265 1.380 1.380 1.375 1.370 1.370 1.345 1.365 1.360 1.350 1.350 1.345 1.440 1.435 1.430 1.430 1.425 1.340 1.335 1.330 1.325 1.320 1.315 1.310 1.300 1.300 1.295 1.390 1.385 1.380 1.375 1.375 Min Typ Max Unit Notes10
Refer to Table 2-7 and Figure 2-4
1.415 1.410 1.405 1.400 1.400
V
1, 2, 3, 4
V
1, 2, 3, 4
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Electrical Specifications
Table 2-6. Voltage and Current Specifications (Sheet 2 of 4)
Symbol Parameter VCC for Processor at VID=1.475 V 2.40C GHz 2.60C GHz 2.80C GHz 3 GHz 3.20C GHz 3.40 GHz VCC for Processor at VID=1.500 V 2.40C GHz 2.60C GHz 2.80C GHz 3 GHz 3.20C GHz 3.40 GHz VCC for Process or at VID=1.525 V 2.40C GHz 2.60C GHz 2.80C GHz 3 GHz 3.20C GHz 3.40 GHz VCC for Processor at VID=1.550 V 3 GHz 3.20C GHz 3.40 GHz Vcc for Processor at VID=1.475 V: 3.20 GHz Vcc for Processor at VID=1.500 V: 3.20 GHz Vcc for Processor at VID=1.525 V 3.20 GHz 3.40 GHz Vcc for Processor at VID=1.550 V 3.20 GHz 3.40 GHz Vcc for Processor at VID=1.575 V 3.40 GHz Vcc for Processor at VID=1.600 V 3.40 GHz VCCVID VCC for voltage identification circuit 1.400 -5% 1.2 1.455 +10% V 9 1.375 1.430 1.360 1.350 1.335 1.325 Refer to Table 2-8 and Figure 2-5 1.390 1.380 V 1.415 1.405 1,2,4,13 1.310 1.365 Min Typ Max Unit Notes10
1.295 1.290 1.288 1.265 1.260 1.280
1.375 1.370 1.369 1.350 1.345 1.350
VCC (800 MHz FSB with 512-KB L2 Cache Only)
1.320 1.315 1.313 1.290 1.285 1.305
Refer to Table 2-7, Figure 2-4. and Table 2-8, Figure 2-5
1.400 1.395 1.394 1.375 1.370 1.375
V
1, 2, 3, 4,13
1.345 1.340 1.338 1.315 1.310 1.330
1.425 1.420 1.419 1.400 1.395 1.400
1.340 1.335 1.355
1.425 1.420 1.425
1.285
1.340
VCC (800 MHz FSB with 2 MB L3 Cache)
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Electrical Specifications
Table 2-6. Voltage and Current Specifications (Sheet 3 of 4)
Symbol Parameter ICC for Processor at VID=1.500 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz ICC for Processor at VID=1.525 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz ICC for Processor with multiple VIDs 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz ICC for Processor at VID=1.500 V 2.26 GHz 2.40B GHz 2.53 GHz ICC for Processor at VID=1.525 V ICC (533 MHz FSB) 2.26 GHz 2.40B GHz 2.53 GHz 2.66 GHz 2.80 GHz ICC for Processor with multiple VIDs 2.26 GHz 2.40B GHz 2.53 GHz 2.66 GHz 2.80 GHz 3.06 GHz ICC (800 MHz FSB with 512-KB L2 Cache Only) ICC (800 MHz FSB with 2-MB L3 Cache) ICC for Processor with multiple VIDs 2.40C GHz 2.60C GHz 2.80C GHz 3 GHz 3.20C GHz 3.40 GHz ICC for Processor with multiple VIDs: 3.20 GHz 3.40 GHz 71.5 77.7 A 4,6,10,13 48.6 50.7 52.5 53.9 55.9 65.4 48.6 50.7 52.5 53.9 55.9 48 49.8 51.5 45.1 47.9 50.7 52.0 53.5 45.1 47.9 50.7 52.0 53.5 A 3,4,6,10 44.3 47.1 49.8 51.3 Min Typ Max Unit Notes10
ICC (400 MHz FSB)
A
3,4,6,10
52.4 55.0 55.9 64.8 67.4 71.6
A
3,4,6,10
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Electrical Specifications
Table 2-6. Voltage and Current Specifications (Sheet 4 of 4)
Symbol Parameter Min Typ Max 23 ISGNT Islp ICC Stop-Grant 27 32 35 ITCC ICC PLL ICC TCC active ICC for PLL pins ICC 60 A mA A Unit Notes10 5,7,8 5,7,11 5,7,12 5,7,14 6
NOTES: 1. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Table 2-2 for more information. The VID bits will set the maximum VCC with the minimum being defined according to current consumption at that voltage. 2. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Refer to Table 2-7 and Figure 2-4 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current. Failure to adhere to this specification can affect the long term reliability of the processor. 4. VCC_MIN is defined at ICC_MAX. 5. The current specified is also for AutoHALT State. 6. The maximum instantaneous current that the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT# is the same as the maximum ICC for the processor. 7. ICC Stop-Grant and ICC Sleep are specified at VCC_MAX. 8. These specifications apply to the processor with maximum VID setting of 1.525 V for the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process. 9. This specification applies to both static and transient components. The rising edge of VCCVID must be monotonic from 0 to 1.1 V. See Figure 2-1 for current requirements. In this case monotonic is defined as continuously increasing with less than 50 mV of peak to peak noise for any width greater than 2 ns superimposed on the rising edge. 10.ICC_MAX is specified for highest VID only. The processor will be shipped under multiple VIDs listed for each frequency; however, the ICC_MAX specifications will be the same as highest VID specified in table. 11. These specifications apply to the processor with maximum VID setting of 1.550 V for the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process. 12.This specification applies to processors with maximum VID setting of 1.550 V for the Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology. 13.Refer to Table 2-8 and Figure 2-5 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCCexceeds VCC_MAX for a given current. Failure to adhere to this specification can affect the long term reliability of the processor. 14.These specifications apply to processors with maximum VID setting of 1.600 V for the Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology.
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Electrical Specifications
Table 2-7. VCC Static and Transient Tolerance (For Intel(R) Pentium(R) 4 Processor With 512-KB L2 Cache on 0.13 Micron Process at Frequencies up to and Including 3.2 GHz)
Voltage Deviation from VID Setting (V)1,2,3 Icc (A) Maximum 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 0.000 -0.010 -0.019 -0.029 -0.038 -0.048 -0.057 -0.067 -0.076 -0.085 -0.095 -0.105 -0.114 -0.124 -0.133 Typical -0.025 -0.036 -0.047 -0.058 -0.069 -0.079 -0.090 -0.101 -0.112 -0.123 -0.134 -0.145 -0.156 -0.166 -0.177 Minimum -0.050 -0.062 -0.075 -0.087 -0.099 -0.111 -0.124 -0.136 -0.148 -0.160 -0.173 -0.185 -0.197 -0.209 -0.222
NOTES: 1. The loadline specifications include both static and transient limits. 2. This table is intended to aid in reading discrete points on the following loadline figure. 3. The loadlines specify voltage limits at the die measured at VCC_SENSE and VSS_SENSE pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to the Intel(R) Pentium(R) 4 Processor VR-Down Design Guidelines for VCC and VSS socket loadline specifications and VR implementation details. 4. Adherence to this loadline specification for the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process is required to ensure reliable processor operation.
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Electrical Specifications
Figure 2-4. VCC Static and Transient Tolerance (For Intel(R) Pentium(R) 4 Processor With 512-KB L2 Cache on 0.13 Micron Process at Frequencies up to and Including 3.2 GHz)
VID +50 mV
VID VCC Maximum VID -50 mV VCC (V)
VID -100 mV VCC Typical
VID -150 mV
VID -200 mV
VCC Minimum
VID -250 mV 0 10 20 30 ICC (A)
40
50
60
70
NOTES: 1. The loadline specification includes both static and transient limits. 2. Refer to Table 2-7 for specific offsets from VID voltage which apply to all VID settings. 3. The loadlines specify voltage limits at the die measured at VCC_SENSE and VSS_SENSE pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to the Intel(R) Pentium(R) 4 Processor VR-Down Design Guidelines VCC and VSS socket loadline specifications and VR implementation details. 4. Adherence to this loadline specification for the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process is required to ensure reliable processor operation.
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Electrical Specifications
Table 2-8. Vcc Static and Transient Tolerance (For Intel(R) Pentium(R) 4 Processor Extreme Edition Supporting Hyper-Threading Technology, and Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process at 3.4 GHz)
Voltage Deviation from VID Setting (V)1,2,3 Icc (A) Maximum 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 0 -0.009 -0.019 -0.028 -0.037 -0.046 -0.056 -0.065 -0.074 -0.083 -0.093 -0.102 -0.111 -0.120 -0.130 -0.139 -0.148 -0.157 -0.167 Typical -0.019 -0.029 -0.039 -0.049 -0.059 -0.068 -0.078 -0.088 -0.098 -0.108 -0.118 -0.128 -0.138 -0.147 -0.157 -0.167 -0.177 -0.187 -0.197 Minimum -0.038 -0.049 -0.059 -0.070 -0.080 -0.091 -0.101 -0.112 -0.122 -0.133 -0.143 -0.154 -0.164 -0.175 -0.185 -0.196 -0.206 -0.217 -0.227
NOTES: 1. The loadline specifications include both static and transient limits. 2. This table is intended to aid in reading discrete points on the following loadline figure. 3. The loadlines specify voltage limits at the die measured at VCC_SENSE and VSS_SENSE pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to the Voltage Regulator-Down (VRD) 10.0 Design Guide Addendum for VCC and VSS socket loadline specifications and VR implementation details. 4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation.
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Electrical Specifications
Figure 2-5. VCC Static and Transient Tolerance (For Intel(R) Pentium(R) 4 Processor Extreme Edition Supporting Hyper-Threading Technology, and Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process at 3.4 GHz)
VID+25 mV VID VID-25 mV VID-50 mV VID-75 mV VCC (Volts) VID-100 mV VID-125 mV VCC Minimum VID-150 mV VID-175 mV VID-200 mV VID-225 mV VID-250 mV 0 10 20 30 40 50 60 70 80 90 ICC (Amperes)
NOTES: 1. The loadline specification includes both static and transient limits. 2. Refer to Table 2-8 for specific offsets from VID voltage which apply to all VID settings. 3. The loadlines specify voltage limits at the die measured at VCC_SENSE and VSS_SENSE pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to the Voltage Regulator-Down (VRD) 10.0 Design Guide Addendum VCC and VSS socket loadline specifications and VR implementation details. 4. Adherence to this loadline specification for the processor is required to ensure reliable processor operation.
VCC Maximum VCC Typical
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Electrical Specifications
.
Table 2-9. AGTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes1
GTLREF GTLREF Compatible VIH VIL VOH IOL IHI ILO RON RON Compatible
Reference Voltage Reference Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Current Pin Leakage High Pin Leakage Low Buffer On Resistance Buffer On Resistance
2/3 VCC - 2% 0.63 VCC - 2% 1.10*GTLREF 0.0 N/A N/A N/A N/A 7 8.4
2/3 VCC + 2% 0.63 VCC +2% VCC 0.9*GTLREF VCC 50 100 500 11 13.2
V V V V V mA A A

10 2,5 3,5 6 5 7 8 4 4, 9
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. Refer to processor I/O Buffer Models for I/V characteristics. 5. The VCC referred to in these specifications is the instantaneous VCC. 6. Vol max of 0.450 V is guaranteed when driving into a test load of 50 as indicated in Figure 2-7. 7. Leakage to VSS with pin held at VCC. 8. Leakage to VCC with Pin held at 300 mV. 9. RON value is defined for a platform that is forward compatible with future processors. 10.GTLREF value is defined for a platform that is forward compatible with future processors.
Table 2-10. Asynchronous GTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes1
VIH VIL VOH IOL IHI ILO Ron RON Compatible
Input High Voltage Asynch GTL+ Input Low Voltage Asynch GTL+ Output High Voltage Output Low Current Pin Leakage High Pin Leakage Low Buffer On Resistance Asynch GTL+ Buffer On Resistance Asynch GTL+
1.10*GTLREF 0
VCC 0.9*GTLREF VCC 50
V V V mA A A

3, 4 4 2, 3 5, 7 8 9 4,6 4,6,10
N/A N/A 7 8.4
100 500 11 13.2
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All outputs are open-drain. 3. The VCC referred to in these specifications refers to instantaneous VCC. 4. This specification applies to the asynchronous GTL+ signal group. 5. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown in Figure 2-7. 6. Refer to the processor I/O Buffer Models for I/V characteristics. 7. Vol max of 0.270 Volts is guaranteed when driving into a test load of 50 as indicated in Figure 2-7 for the Asynchronous GTL+ signals. 8. Leakage to VSS with pin held at VCC. 9. Leakage to VCC with Pin held at 300 mV. 10.RON value is defined for a platform that is forward compatible with future processors.
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Electrical Specifications
Table 2-11. PWRGOOD and TAP Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes1
VHYS VT+ VTVOH IOL IHI ILO RON
Input Hysteresis Input Low to High Threshold Voltage Input High to Low Threshold Voltage Output High Voltage Output Low Current Pin Leakage High Pin Leakage Low Buffer On Resistance
200 1/2*(VCC+VHYS_MIN) 1/2*(VCC-VHYS_MAX) N/A N/A N/A N/A 8.75
300 1/2*(VCC+VHYS_MAX) 1/2*(VCC-VHYS_MIN) VCC 40 100 500 13.75
mV V V V mA A A
6 4 5 2,3,4 5,6 8 9 3
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All outputs are open-drain. 3. Refer to I/O Buffer Models for I/V characteristics. 4. The VCC referred to in these specifications refers to instantaneous VCC. 5. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load shown in Figure 2-7. 6. Vol max of 0.320 V is guaranteed when driving into a test load of 50 as indicated in Figure 2-7 for the TAP Signals. 7. VHYS represents the amount of hysteresis, nominally centered about 1/2 VCC for all TAP inputs. 8. Leakage to VSS with pin held at VCC. 9. Leakage to VCC with Pin held at 300 mV.
Table 2-12. ITPCLKOUT[1:0] DC Specifications
Symbol Parameter Min Max Unit Notes1
Ron
Buffer On Resistance
27
46
2,3
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. See Figure 2-6 for ITPCLKOUT[1:0] output buffer diagram.
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Electrical Specifications
Figure 2-6. ITPCLKOUT[1:0] Output Buffer Diagram
VCC
Ron
To Debug Port Processor Package
Rext
NOTES: 1. See Table 2-12 for range of Ron. 2. The VCC referred to in this figure is the instantaneous Vcc. 3. Refer to the ITP 700 Debug Port Design Guide and the appropriate platform design guidelines for the value of Rext.
Table 2-13. BSEL [1:0] and VID[4:0] DC Specifications
Symbol Parameter Min Max Unit Notes1
Ron (BSEL) Ron (VID) IHI
Buffer On Resistance Buffer On Resistance Pin Leakage High
9.2 7.8 N/A
14.3 12.8 100
2 2 3
A
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are not tested and are based on design simulations. 3. Leakage to Vss with pin held at 2.50 V.
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Electrical Specifications
2.12
AGTL+ System Bus Specifications
Routing topology recommendations may be found in the appropriate platform design guide listed in Table 1-1. Termination resistors are not required for most AGTL+ signals because they are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal's voltage with a reference voltage called GTLREF (known as VREF in previous documentation). Table 2-14 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. It is important that the system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance for the AGTL+ signal group traces is known and is well-controlled. For more details on platform design, see the appropriate platform design guide.
Table 2-14. AGTL+ Bus Voltage Definitions
Symbol Parameter Min Typ Max Units Notes1
GTLREF GTLREF Compatible RTT RTT Compatible COMP[1:0] COMP[1:0] Compatible
Bus Reference Voltage Bus Reference Voltage Termination Resistance Termination Resistance COMP Resistance COMP Resistance
2/3 VCC -2% 0.63 VCC -2% 45 54 50.49 61.3
2/3 VCC 0.63 VCC 50 60 51 61.9
2/3 VCC +2% 0.63 VCC +2% 55 66 51.51 62.5

V V
2, 3, 6 2, 3, 6, 7 4 4, 7
5 5, 7
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of VCC. 3. GTLREF should be generated from VCC by a voltage divider of 1% tolerance resistors or 1% tolerance, matched resistors. Refer to the appropriate Platform Design Guide for implementation details. 4. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor I/O buffer models for I/V characteristics. 5. COMP resistance must be provided on the system board with 1% tolerance resistors. See the appropriate Platform Design Guide for implementation details. 6. The VCC referred to in these specifications is the instantaneous VCC. 7. The specifications are for a platform to be forward compatible with future processors. A compatible platform is one that is designed for some level of compatibility with future processors.
Figure 2-7. Test Circuit
VCC VCC 420 mils, 50 , 169 ps/in 2.4 nH Rload = 50
1.2 pF
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Electrical Specifications
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Package Mechanical Specifications
Package Mechanical Specifications
3
The Pentium 4 processor on 0.13 micron process is packaged in a Flip-Chip Pin Grid Array (FC-PGA2) package. Components of the package include an integrated heat spreader (IHS), processor die, and the substrate which is the pin carrier. Mechanical specifications for the processor are given in this section. See Section 1.1. for a terminology listing. The processor socket that accepts the Pentium 4 processor on 0.13 micron process is referred to as a 478-Pin micro PGA (mPGA478B) socket. See the Intel(R) Pentium(R) 4 Processor 478-Pin Socket (mPGA478B) Socket Design Guidelines for complete details on the mPGA478B socket. Note: For Figure 3-1 through Figure 3-8, the following notes apply: 1. Unless otherwise specified, the following drawings are dimensioned in millimeters. 2. Figures and drawings labelled as "Reference Dimensions" are provided for informational purposes only. Reference dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied. Reference dimensions are not checked as part of the processor manufacturing process. Unless noted as such, dimensions in parentheses without tolerances are reference dimensions. 3. Drawings are not to scale. Note: Figure 3-1 is not to scale and is for reference only. The socket and system board are supplied as a reference only.
Figure 3-1. Exploded View of Processor Components on a System Board
Heat Spreader
31 mm
3.5m m
Substrate
2.0m m 35m m square 478 pins
mPGA478B Socket
System board
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Package Mechanical Specifications
Figure 3-2. Processor Package
Table 3-1. Description Table for Processor Dimensions
Dimension (mm) Code Letter Min Nominal Max Notes
A1 A2 A1 A2 B1 B2 C1 C2 D D1 G1 G2 G3 H L
P
2.266 0.980 2.42 1.13 30.800 30.800
2.378 1.080 2.55 1.20 31.000 31.000
2.490 1.180 2.67 1.27 31.200 31.200 33.000 33.000
Original package (6 layer) Original package (6 layer) Alternate equivalent package (8 layer) Alternate equivalent package (8 layer)
Includes placement tolerance Includes placement tolerance
34.900 31.500
35.000 31.750
35.100 32.000 13.970 13.970 1.250 Keep-In Zone dimension Keep-In Zone dimension Keep-In Zone dimension
1.270 1.950 0.280 2.030 0.305 2.110 0.330 0.254 0.05 Diametric True Position (Pin-to-Pin)
PIN TP IHS Flatness
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Package Mechanical Specifications
Figure 3-3 details the keep-in specification for pin-side components. The Pentium 4 processor on 0.13 micron process may contain pin-side capacitors mounted to the processor package. Figure 3-5 details the flatness and tilt specifications for the IHS. Tilt is measured with the reference datum set to the bottom of the processor susbstrate. Figure 3-3. Processor Cross-Section and Keep-In
FCPGA 2 IHS Substrate 13.97m m Com ponent Keepin Socket must allow clearance for pin shoulders and m ate flush with this surface 1.25mm
Figure 3-4. Processor Pin Detail
O 0.65 MAX PINHEAD DIAMETER
O 0.3050.025
O 1.032 MAX KEEP OUT ZONE
0.3 MAX SOLDER FILLET HEIGHT 2.030.08 ALL DIMENSIONS ARE IN MILIMETERS
NOTES: 1. Pin plating consists of 0.2 micrometers Au over 2.0 micrometer Ni. 2. 0.254 mm diametric true position, pin-to-pin.
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Package Mechanical Specifications
Figure 3-5. IHS Flatness Specification
IHS
SUBSTRATE
NOTES: 1. Flatness is specific as overall, not per unit of length. 2. All Dimensions are in millimeters.
3.1
Package Load Specifications
Table 3-2 provides dynamic and static load specifications for the processor IHS. These mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing, or standard drop and shipping conditions. The heatsink attach solutions must not induce continuous stress onto the processor with the exception of a uniform load to maintain the heatsink-to-processor thermal interface contact. It is not recommended to use any portion of the processor substrate as a mechanical reference or load bearing surface for thermal solutions.
Table 3-2. Package Dynamic and Static Load Specifications
Parameter Max Unit Notes
Static Dynamic
100 200
lbf lbf
1, 2 1, 3
NOTES: 1. This specification applies to a uniform compressive load. 2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface. 3. Dynamic loading specifications are defined assuming a maximum duration of 11 ms and 200 lbf is achieved by superimposing a 100 lbf dynamic load (1 lbm at 50 g) on the static compressive load.
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Package Mechanical Specifications
3.2
Processor Insertion Specifications
The Pentium 4 processor on 0.13 micron process can be inserted and removed 15 times from a mPGA478B socket meeting the Intel(R) Pentium(R) 4 Processor 478-Pin Socket (mPGA478B) Socket Design Guidelines document.
3.3
Processor Mass Specifications
Table 3-3 specifies the processor's mass. This includes all components which make up the entire processor product.
Table 3-3. Processor Mass
Processor Mass (grams)
Intel(R) Pentium(R) 4 processor on 0.13 micron process
19
3.4
Processor Materials
The Pentium 4 processor on 0.13 micron process is assembled from several components. The basic material properties are described in Table 3-4.
Table 3-4. Processor Material Properties
Component Material
Integrated Heat Spreader Substrate Substrate pins
Nickel over copper Fiber-reinforced resin Gold over nickel
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Package Mechanical Specifications
3.5
Processor Markings
Figure 3-6 and Figure 3-7 detail the processor top-side markings and is provided to aid in the identification of the Pentium 4 processors on 0.13 micron process.
Figure 3-6. Processor Markings (Processors with Fixed VID)
INTEL m c 01 PENTIUM(R) 4
2.40 GHZ/512/800/1.50V
Frequency/Cache/Bus/Voltage
S-Spec/Country of Assy FPO - Serial #
SYYYY XXXXXX FFFFFFFF-NNNN
2-D Matrix Mark
Figure 3-7. Processor Markings (Processors with Multiple VID)
INTEL m c 01 PENTIUM(R) 4
2.40 GHZ/512/800
Frequency/Cache/Bus
S-Spec/Country of Assy FPO - Serial #
SYYYY XXXXXX FFFFFFFF-NNNN
2-D Matrix Mark
INTEL m c 03 PENTIUM(R) 4
2.40 GHZ/512/800
Frequency/Cache/Bus
S-Spec/Country of Assy FPO 2-D Matrix Mark
SYYYY XXXXXX FFFFFFFF AAAAAAAA NNNN
unique unit identifier ATPO Serial #
NOTE: Intel will continue to ship old and new marked parts until old mark inventory has been depleted.
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Package Mechanical Specifications
Figure 3-8. The Coordinates of the Processor Pins As Viewed from the Top of the Package
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Pin Lists and Signal Descriptions
Pin Lists and Signal Descriptions
4.1 Processor Pin Assignments
This section contains pin lists for the Pentium 4 processor on 0.13 micron process. Table 4-1 is ordered alphabetically by pin name; Table 4-2 is ordered alphabetically by pin number.
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Pin Lists and Signal Descriptions
Table 4-1. Pin Listing by Pin Name
Pin Name A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# A20M# ADS# ADSTB0# ADSTB1# AP0# AP1# BCLK0 BCLK1 BINIT# BNR# BPM0# Pin Number K2 K4 L6 K1 L3 M6 L2 M3 M4 N1 M1 N2 N4 N5 T1 R2 P3 P4 R3 T2 U1 P6 U3 T4 V2 R6 W1 T5 U4 V3 W2 Y1 AB1 C6 G1 L5 R5 AC1 V5 AF22 AF23 AA3 G2 AC6 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Asynch GTL+ Common Clock Source Synch Source Synch Common Clock Common Clock Bus Clock Bus Clock Common Clock Common Clock Common Clock Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output
Table 4-1. Pin Listing by Pin Name
Pin Name BPM1# BPM2# BPM3# BPM4# BPM5# BPRI# BR0# BSEL0 BSEL1 COMP0 COMP1 D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# Pin Number AB5 AC4 Y6 AA5 AB4 D2 H6 AD6 AD5 L24 P1 B21 B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23 J21 D25 H22 E24 G23 F23 F24 E25 F26 D26 L21 G26 H24 M21 L22 J24 K23 H25 M23 Signal Buffer Type Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
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Pin Lists and Signal Descriptions
Table 4-1. Pin Listing by Pin Name
Pin Name D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBI0# DBI1# DBI2# DBI3# DBR# DBSY# DEFER# DP0# DP1# DP2# DP3# DRDY# DSTBN0# Pin Number N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24 E21 G25 P26 V21 AE25 H5 E2 J26 K25 K26 L25 H2 E22 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Power/Other Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Common Clock Source Synch Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Table 4-1. Pin Listing by Pin Name
Pin Name DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FERR# GTLREF GTLREF GTLREF GTLREF HIT# HITM# IERR# IGNNE# Pin Number K22 R22 W22 F21 J23 P23 W23 B6 AA21 AA6 F20 F6 F3 E3 AC3 B2 Signal Buffer Type Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Source Synch Asynch AGL+ Power/Other Power/Other Power/Other Power/Other Common Clock Common Clock Common Clock Asynch GTL+ Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Input Input Input/Output Input/Output Output Input
IMPSEL
INIT# ITPCLKOUT0 ITPCLKOUT1 ITP_CLK0 ITP_CLK1 LINT0 LINT1 LOCK# MCERR# PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESET# RS0# RS1#
AE26
W5 AA20 AB22 AC26 AD26 D1 E5 G4 V6 C3 AB23 J1 K5 J4 J3 H3 A22 A7 AD2 AD3 AE21 AF3 AF24 AF25 AB25 F1 G5
Power/Other
Asynch GTL+ Power/Other Power/Other TAP TAP Asynch GTL+ Asynch GTL+ Common Clock Common Clock Asynch GTL+ Power/Other Source Synch Source Synch Source Synch Source Synch Source Synch
Input
Input Output Output input input Input Input Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output
Common Clock Common Clock Common Clock
Input Input Input
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Pin Lists and Signal Descriptions
Table 4-1. Pin Listing by Pin Name
Pin Name RS2# RSP# SKTOCC# SLP# SMI# STPCLK# TCK TDI TDO TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI8 TESTHI9 TESTHI10 TESTHI11 TESTHI12 THERMDA THERMDC THERMTRIP# TMS TRDY# TRST# VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Number F4 AB2 AF26 AB26 B5 Y4 D4 C1 D5 AD24 AA2 AC21 AC20 AC24 AC23 U6 W4 Y3 A6 AD25 B3 C4 A2 F7 J6 E6 A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 Signal Buffer Type Common Clock Common Clock Power/Other Asynch GTL+ Asynch GTL+ Asynch GTL+ TAP TAP TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Asynch GTL+ TAP Common Clock TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Input Input Direction Input Input Output Input Input Input Input Input Output Input Input Input Input Input Input Input Input Input Input Input
Table 4-1. Pin Listing by Pin Name
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Pin Number AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19 AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 AF15 AF17 AF19 AF2 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
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Pin Lists and Signal Descriptions
Table 4-1. Pin Listing by Pin Name
Pin Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCA VCCIOPLL VCC_SENSE VCCVID VID0 VID1 VID2 VID3 VID4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number C18 C20 C8 D11 D13 D15 D17 D19 D7 D9 E10 E12 E14 E16 E18 E20 E8 F11 F13 F15 F17 F19 F9 AD20 AE23 A5 AF4 AE5 AE4 AE3 AE2 AE1 D10 A11 A13 A15 A17 A19 A21 A24 A26 A3 A9 AA1 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Input Output Output Output Output Output Direction
Table 4-1. Pin Listing by Pin Name
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number AA11 AA13 AA15 AA17 AA19 AA23 AA26 AA4 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB21 AB24 AB3 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC2 AC22 AC25 AC5 AC7 AC9 AD1 AD10 AD12 AD14 AD16 AD18 AD21 AD23 AD4 AD8 AE11 AE13 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Pin Lists and Signal Descriptions
Table 4-1. Pin Listing by Pin Name
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number AE15 AE17 AE19 AE22 AE24 AE7 AE9 AF1 AF10 AF12 AF14 AF16 AF18 AF20 AF6 AF8 B10 B12 B14 B16 B18 B20 B23 B26 B4 B8 C11 C13 C15 C17 C19 C2 C22 C25 C5 C7 C9 D12 D14 D16 D18 D20 D21 D24 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table 4-1. Pin Listing by Pin Name
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number D3 D6 D8 E1 E11 E13 E15 E17 E19 E23 E26 E4 E7 E9 F10 F12 F14 F16 F18 F2 F22 F25 F5 F8 G21 G24 G3 G6 H1 H23 H26 H4 J2 J22 J25 J5 K21 K24 K3 K6 L1 L23 L26 L4 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
50
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Pin Lists and Signal Descriptions
Table 4-1. Pin Listing by Pin Name
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Pin Number M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25 P5 R1 R23 R26 R4 T21 T24 T3 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table 4-1. Pin Listing by Pin Name
Pin Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSA VSS_SENSE Pin Number T6 U2 U22 U25 U5 V1 V23 V26 V4 W21 W24 W3 W6 Y2 Y22 Y25 Y5 AD22 A4 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Direction
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
51
Pin Lists and Signal Descriptions
Table 4-2. Pin Listing by Pin Number
Pin Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 Pin Name THERMTRIP# VSS VSS_SENSE VCC_SENSE TESTHI11 RESERVED VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS RESERVED D2# VSS D3# VSS VSS TESTHI1 BINIT# VSS BPM4# GTLREF VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS Source Synch Power/Other Source Synch Power/Other Power/Other Power/Other Common Clock Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output Input Input Input/Output Input/Output Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Signal Buffer Type Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Output Output Input Direction Output
Table 4-2. Pin Listing by Pin Number
Pin Number AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 Pin Name ITPCLK[0] GTLREF D62# VSS D63# D61# VSS A35# RSP# VSS BPM5# BPM1# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS ITPCLK[1] PWRGOOD VSS RESET# SLP# AP#[0] VSS IERR# BPM2# VSS BPM0# VSS VCC VSS VCC VSS Signal Buffer Type Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Common Clock Power/Other Common Clock Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Asynch GTL+ Common Clock Power/Other Common Clock Common Clock Power/Other Common Clock Power/Other Power/Other Power/Other Power/Other Power/Other Input/Output Output Input/Output Input Input Input/Output Output Input Input/Output Input/Output Input/Output Input Input/Output Input/Output Direction Output Input Input/Output
52
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Pin Lists and Signal Descriptions
Table 4-2. Pin Listing by Pin Number
Pin Number AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 Pin Name VCC VSS VCC VSS VCC VSS VCC VSS TESTHI3 TESTHI2 VSS TESTHI5 TESTHI4 VSS ITP_CLK0 VSS RESERVED RESERVED VSS BSEL1 BSEL0 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCCA VSS VSSA VSS TESTHI0 TESTHI12 ITP_CLK1 VID4 VID3 VID2 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other Power/Other Power/Other Input Input input Output Output Output Output Output Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other TAP Power/Other input Input Input Input Input Direction
Table 4-2. Pin Listing by Pin Number
Pin Number AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 Pin Name VID1 VID0 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC RESERVED VSS VCCIOPLL VSS DBR# IMPSEL VSS VCC RESERVED VCCVID VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Power/Other Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Power/Other Output Input Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction Output Output
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
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Pin Lists and Signal Descriptions
Table 4-2. Pin Listing by Pin Number
Pin Number AF22 AF23 AF24 AF25 AF26 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Pin Name BCLK[0] BCLK[1] RESERVED RESERVED SKTOCC# IGNNE# THERMDA VSS SMI# FERR# VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D0# D01# VSS D6# D9# VSS TDI VSS PROCHOT# THERMDC VSS A20M# VSS VCC VSS VCC VSS VCC VSS VCC Power/Other Asynch GTL+ Power/Other Power/Other Asynch GTL+ Asynch AGL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other TAP Power/Other Asynch GTL+ Power/Other Power/Other Asynch GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input/Output Input Input/Output Input/Output Input/Output Input/Output Input Output Output Input Signal Buffer Type Bus Clock Bus Clock Direction Input Input
Table 4-2. Pin Listing by Pin Number
Pin Number C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 Pin Name VSS VCC VSS VCC VSS VCC D4# VSS D7# D8# VSS D12# LINT0 BPRI# VSS TCK TDO VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS D5# D13# VSS D15# D23# VSS DEFER# HITM# VSS LINT1 TRST# Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Asynch GTL+ Common Clock Power/Other TAP TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Power/Other Asynch GTL+ TAP Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Output Input/Output Input Input Input/Output Input/Output Input/Output Direction
54
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Pin Lists and Signal Descriptions
Table 4-2. Pin Listing by Pin Number
Pin Number E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 Pin Name VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC DBI0# DSTBN0# VSS D17# D21# VSS RS0# VSS HIT# RS2# VSS GTLREF TMS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC GTLREF DSTBP0# VSS D19# D20# Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Power/Other Common Clock Common Clock Power/Other Power/Other TAP Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Input/Output Input/Output Input Input/Output Input Input Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Direction
Table 4-2. Pin Listing by Pin Number
Pin Number F25 F26 G1 G2 G3 G4 G5 G6 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 Pin Name VSS D22# ADS# BNR# VSS LOCK# RS1# VSS VSS D10# D18# VSS DBI1# D25# VSS DRDY# REQ4# VSS DBSY# BR0# D11# D16# VSS D26# D31# VSS REQ0# VSS REQ3# REQ2# VSS TRDY# D14# VSS DSTBP1# D29# VSS DP0# A6# A3# VSS A4# REQ1# VSS Signal Buffer Type Power/Other Source Synch Common Clock Common Clock Power/Other Common Clock Common Clock Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Power/Other Common Clock Common Clock Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Direction
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
55
Pin Lists and Signal Descriptions
Table 4-2. Pin Listing by Pin Number
Pin Number K21 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M21 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N6 N21 N22 N23 N24 N25 N26 P1 P2 Pin Name VSS DSTBN1# D30# VSS DP1# DP2# VSS A9# A7# VSS ADSTB0# A5# D24# D28# VSS COMP0 DP3# VSS A13# VSS A10# A11# VSS A8# D27# VSS D32# D35# VSS D37# A12# A14# VSS A15# A16# VSS VSS D33# D36# VSS D39# D38# COMP1 VSS Signal Buffer Type Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Source Synch Power/Other Power/Other Common Clock Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction
Table 4-2. Pin Listing by Pin Number
Pin Number P3 P4 P5 P6 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U21 U22 U23 U24 Pin Name A19# A20# VSS A24# D34# VSS DSTBP2# D41# VSS DBI2# VSS A18# A21# VSS ADSTB1# A28# D40# DSTBN2# VSS D43# D42# VSS A17# A22# VSS A26# A30# VSS VSS D46# D47# VSS D45# D44# A23# VSS A25# A31# VSS TESTHI8 D52# VSS D50# D49# Signal Buffer Type Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Source Synch Power/Other Source Synch Source Synch Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction Input/Output Input/Output
56
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Pin Lists and Signal Descriptions
Table 4-2. Pin Listing by Pin Number
Pin Number U25 U26 V1 V2 V3 V4 V5 V6 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 Pin Name VSS D48# VSS A27# A32# VSS AP1# MCERR# DBI3# D53# VSS D54# D51# VSS A29# A33# VSS TESTHI9 INIT# Signal Buffer Type Power/Other Source Synch Power/Other Source Synch Source Synch Power/Other Common Clock Common Clock Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Power/Other Power/Other Asynch GTL+ Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Direction
Table 4-2. Pin Listing by Pin Number
Pin Number W6 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y21 Y22 Y23 Y24 Y25 Y26 Pin Name VSS VSS DSTBN3# DSTBP3# VSS D57# D55# A34# VSS TESTHI10 STPCLK# VSS BPM3# D60# VSS D58# D59# VSS D56# Signal Buffer Type Power/Other Power/Other Source Synch Source Synch Power/Other Source Synch Source Synch Source Synch Power/Other Power/Other Asynch GTL+ Power/Other Common Clock Source Synch Power/Other Source Synch Source Synch Power/Other Source Synch Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Direction
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
57
Pin Lists and Signal Descriptions
4.2
Signal Descriptions
Table 4-3. Signal Descriptions (Sheet 1 of 8)
Name Type Description
A[35:3]#
Input/ Output
A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Intel(R) Pentium(R) 4 processor on 0.13 micron process system bus. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# pins to determine power-on configuration. See Section 6.1 for more details. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.
A20M#
Input
ADS#
Input/ Output
ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.
ADSTB[1:0]#
Input/ Output
Signals
Associated Strobe
REQ[4:0]#, A[16:3]# A[35:17]#
ADSTB0# ADSTB1#
AP[1:0]#
Input/ Output
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#, A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all Pentium 4 processors on 0.13 micron process system bus agents. The following table defines the coverage model of these signals.
Request Signals Subphase 1 Subphase 2
A[35:24]# A[23:3]# REQ[4:0]#
AP0# AP1# AP1#
AP1# AP0# AP0#
BCLK[1:0]
Input
The differential pair BCLK (Bus Clock) determines the system bus frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
58
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Pin Lists and Signal Descriptions
Table 4-3. Signal Descriptions (Sheet 2 of 8)
Name Type Description
BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. Input/ Output If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT# activation. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the system bus and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system. BNR# Input/ Output BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions. BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all Pentium 4 processors on 0.13 micron process system bus agents. BPM[5:0]# Input/ Output BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. Refer to the appropriate Platform Design Guide for more detailed information. These signals do not have on-die termination and must be terminated on the system board. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of all processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this pin is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. BSEL[1:0] (Bus Select) are used to select the processor input clock frequency. Table 2-4 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. For more information about these pins, including termination recommendations refer to Section 2.9 and the appropriate platform design guidelines. COMP[1:0] must be terminated on the system board using precision resistors. Refer to the appropriate Platform Design Guide for details on implementation.
BINIT#
BPRI#
Input
BR0#
Input/ Output
BSEL[1:0]
Input/ Output
COMP[1:0]
Analog
Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
59
Pin Lists and Signal Descriptions
Table 4-3. Signal Descriptions (Sheet 3 of 8)
Name Type Description
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#. D[63:0]# Input/ Output
Quad-Pumped Signal Groups
Data Group
DSTBN#/ DSTBP#
DBI#
D[15:0]# D[31:16]# D[47:32]# D[63:48]#
0 1 2 3
0 1 2 3
Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits within a 16-bit group would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group. DBI[3:0]# Input/ Output
DBI[3:0]# Assignment To Data Bus
Bus Signal
Data Bus Signals
DBI3# DBI2# DBI1# DBI0#
D[63:48]# D[47:32]# D[31:16]# D[15:0]#
DBR#
Output
DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on all processor system bus agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of all processor system bus agents. DP[3:0]# (Data parity) provide parity protection for the D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all Pentium 4 processor on 0.13 micron process system bus agents.
DBSY#
Input/ Output
DEFER#
Input
DP[3:0]#
Input/ Output
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Pin Lists and Signal Descriptions
Table 4-3. Signal Descriptions (Sheet 4 of 8)
Name Type Description
DRDY#
Input/ Output
DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor system bus agents. Data strobe used to latch in D[63:0]#:
Signals Associated Strobe
DSTBN[3:0]#
Input/ Output
D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3# Data strobe used to latch in D[63:0]#:
Signals
DSTBN0# DSTBN1# DSTBN2# DSTBN3#
Associated Strobe
DSTBP[3:0]#
Input/ Output
D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3#
DSTBP0# DSTBP1# DSTBP2# DSTBP3#
FERR#/PBE#
Output
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal which is qualified by STPCLK#. When STPCLK# is not asserted, FERR# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using Microsoft MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. For addition information on the pending break event functionality, including the identification of support of the feature and enable/disable information, refer to the IA-32 Intel(R) Architecture Software Developer's Manual (Vol. 1 - Vol. 3) and the Intel (R) Processor Identification and the CPUID Instruction application note. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCC. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. Refer to the appropriate Platform Design Guide for more information. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#. This signal does not have on-die termination and must be terminated on the system board.
GTLREF
Input Input/ Output Input/ Output
HIT# HITM#
IERR#
Output
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Pin Lists and Signal Descriptions
Table 4-3. Signal Descriptions (Sheet 5 of 8)
Name Type Description
IGNNE#
Input
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.
IMPSEL
Input
IMPSEL input will determine whether the processor uses a 50 or 60 buffer. This pin must be tied to GND on 50 platforms and left as NC on 60 platforms. INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). ITPCLKOUT[1:0] is an uncompensated differential clock output that is a delayed copy of BCLK[1:0], which is an input to the processor. This clock output can be used as the differential clock into the ITP port that is designed onto the motherboard. If ITPCLKOUT[1:0] outputs are not used, they must be terminated properly. Refer to Section 2.5 for additional details and termination requirements. Refer to the ITP 700 Debug Port Design Guide for details on implementing a debug port. ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock.
INIT#
Input
ITPCLKOUT[1:0]
Output
ITP_CLK[1:0]
Input
LINT[1:0]
Input
LOCK#
Input/ Output
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Pin Lists and Signal Descriptions
Table 4-3. Signal Descriptions (Sheet 6 of 8)
Name Type Description
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: MCERR# Input/ Output * Enabled or disabled. * Asserted, if configured, for internal errors along with IERR#. * Asserted, if configured, by the request initiator of a bus transaction after it observes an error. * Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, refer to the IA-32 Intel(R) Software Developer's Manual, Volume 3: System Programming Guide. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the system deasserts PROCHOT#. See Section 6.3 for more details.
NOTE: The PROCHOT# signal functionality has changed from output to input/output on CPUID 0xF27 and beyond.
PROCHOT#
Input/ Output
PWRGOOD
Input
PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. `Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.
REQ[4:0]#
Input/ Output
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for details on parity checking of these signals. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These configuration options are described in the Section 6.1. This signal does not have on-die termination and must be terminated on the system board.
RESET#
Input
RS[2:0]#
Input
RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents.
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Pin Lists and Signal Descriptions
Table 4-3. Signal Descriptions (Sheet 7 of 8)
Name Type Description
RSP#
Input
RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor system bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this pin to determine if the processor is present. SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will only recognize the assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enters System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. Assertion of STPCLK# (Stop Clock) causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC power source through a resistor for proper processor operation. See Section 2.5 for more details. Thermal Diode Anode. See Section 6.3.1. Thermal Diode Cathode. See Section 6.3.1.
SKTOCC#
Output
SLP#
Input
SMI#
Input
STPCLK#
Input
TCK TDI TDO TESTHI[12:8] TESTHI[5:0] THERMDA THERMDC
Input Input Output Input Other Other
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Pin Lists and Signal Descriptions
Table 4-3. Signal Descriptions (Sheet 8 of 8)
Name Type Description
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level where permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135C. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must be removed within 0.5 seconds of the assertion of THERMTRIP#. For processors with CPUID of 0xF24: THERMTRIP# Output * Once activated, THERMTRIP# remains latched until RESET# is asserted. While the assertion of the RESET# signal will de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted. For processors with CPUID of 0xF27 and beyond: * Driving of the THERMTRIP# signal is enabled within 10 s of the assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated, THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the processor's junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 s of the assertion of PWRGOOD. TMS TRDY# Input Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. This can be done with a 680 pull-down resistor. VCCA provides isolated power for the internal processor core PLLs. Refer to the appropriate Platform Design Guide for complete implementation details. VCCIOPLL provides isolated power for internal processor system bus PLLs. Follow the guidelines for VCCA, and refer to the appropriate Platform Design Guide for complete implementation details. VCC_SENSE is an isolated low impedance connection to processor core power (VCC). It can be used to sense or measure power near the silicon with little noise. Independent 1.2 V supply must be routed to VCCVID pin for the Pentium 4 processor on 0.13 micron process's Voltage Identification circuit. VID[4:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). Unlike previous generations of processors, these are open drain signals that are driven by the Pentium 4 processor on 0.13 micron process and must be pulled up to 3.3 V (max.) with 1 k resistors. The voltage supply for these pins must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 2-2 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself. VSSA is the isolated ground for internal PLLs. VSS_SENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise
TRST# VCCA VCCIOPLL VCC_SENSE VCCVID
Input Input Input Output Input
VID[4:0]
Output
VSSA VSS_SENSE
Input Output
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Thermal Specifications and Design Considerations
Thermal Specifications and Design Considerations
5
The Pentium 4 processor on 0.13 micron process uses an Integrated Heat Spreader (IHS) for heatsink attachment that is intended to provide for multiple types of thermal solutions. This chapter provides data necessary for development of a thermal solution. See Figure 5-1 for an enlarged view of an example of the Pentium 4 processor on 0.13 micron process thermal solution. This is for illustration purposes only. For further thermal solution design details, refer to the. Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines. Note: The processor is shipped either by itself or with a heatsink for boxed processors. See Chapter 7 for details on boxed processors.
Figure 5-1. Example Thermal Solution (Not to Scale)
Clip Assembly
Fan/Shroud
Heatsink
Retention Mechanism Processor mPGA478B 478-pin Socket
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Thermal Specifications and Design Considerations
5.1
Processor Thermal Specifications
The Pentium 4 processor on 0.13 micron process requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component-level thermal solutions can include active or passive heatsinks attached to the processor IHS. Typical system level thermal solutions may consist of system fans combined with ducting and venting. For more information on designing a component level thermal solution, refer to Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines.
5.1.1
Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (TC) specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 5-1. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate processor thermal design guidelines. The case temperature is defined at the geometric top center of the processor IHS. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption. The Thermal Monitor feature is intended to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 6.3. To ensure maximum flexibility for future requirements, systems should be designed to the Flexible Motherboard (FMB) guidelines, even if a processor with a lower thermal dissipation is currently planned. In all cases, the Thermal Monitor feature must be enabled for the processor to remain within specification.
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Thermal Specifications and Design Considerations
Table 5-1. Processor Thermal Design Power
Front Side Bus Frequency Processor and Core Frequency Processors with VID=1.500 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz Processors with VID=1.525 V Thermal Design Power1,2 (W) Minimum TC (C) Maximum TC (C) Notes3
52.4 55.1 57.8 59.3
5 5 5 5
68 69 70 71
400 MHz
2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz
Processors with multiple VIDs
54.3 57.1 59.8 61.0 62.6
5 5 5 5 5
69 70 71 72 72
2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz
Processors with VID=1.500 V
54.3 57.1 59.8 61.0 62.6
5 5 5 5 5
69 70 71 72 72
2.26 GHz 2.40B GHz 2.53 GHz
Processors with VID=1.525 V
56.0 57.8 59.3
5 5 5
70 70 71
533 MHz
2.26 GHz 2.40B GHz 2.53 GHz 2.66 GHz 2.80 GHz
Processors with multiple VIDs
58.0 59.8 61.5 66.1 68.4
5 5 5 5 5
70 71 72 74 75
2.26 GHz 2.40B GHz 2.53 GHz 2.66 GHz 2.80 GHz 3.06 GHz
Processors with multiple VIDs
58.0 59.8 61.5 66.1 68.4 81.8
5 5 5 5 5 5
70 71 72 74 75 69
800 MHz FSB with 512-KB L2 Cache Only
2.40C GHz 2.60C GHz 2.80C GHz 3 GHz 3.20C GHz 3.40 GHz
Processors with multiple VIDs 3.20 GHz 3.40 GHz
66.2 69.0 69.7 81.9 82.0 89.0
5 5 5 5 5 5
74 75 75 70 70 68
800 MHz FSB with 2-MB L3 Cache
92.1 102.9
5 5
64 67
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Thermal Specifications and Design Considerations
NOTES: 1. These values are specified at VCC_MAX for the processor. Systems must be designed to ensure that the processor is not subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Refer to loadline specifications in Chapter 2. 2. The numbers in this column reflect Intel's recommended design point and are not indicative of the maximum power the processor can dissipate under worst case conditions. For more details, refer to the Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines. 3. TDP and TC are specified for highest VID only. Processors will be shipped under multiple VIDs for each frequency; however, the TDP and TC specifications will be the same as highest VID specified in the table.
5.1.2
5.1.2.1
Thermal Metrology
Processor Case Temperature Measurement
The maximum and minimum case temperature (TC) for the Pentium 4 processor on 0.13 micron process is specified in Table 5-1. This temperature specification is meant to help ensure proper operation of the processor. Figure 5-2 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel(R) Pentium(R) Processor 4 with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines.
Figure 5-2. Guideline Locations for Case Temperature (TC) Thermocouple Placement
0.689" 17.5 mm
Measure Tcase At this point
0.689" 17.5 mm
35 mm Package
Thermal Interface Material should cover the entire surface of the Integrated Heat Spreader
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Features
Features
6.1 Power-On Configuration Options
6
Several configuration options can be configured by hardware. The Pentium 4 processor on 0.13 micron process samples hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset. Table 6-1. Power-On Configuration Option Pins
Configuration Option Pin1
Output tristate Execute BIST In Order Queue pipelining (set IOQ depth to 1) Disable MCERR# observation Disable BINIT# observation APIC Cluster ID (0-3) Disable bus parking Disable Hyper-Threading Technology Symmetric agent arbitration ID
SMI# INIT# A7# A9# A10# A[12:11]# A15# A31# BR0#
NOTE: 1. Asserting this signal during RESET# will select the corresponding option.
6.2
Clock Control and Low Power States
The use of AutoHALT, Stop-Grant, and Sleep states is allowed in Pentium 4 processor on 0.13 micron process-based systems to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 6-1 for a visual representation of the processor low power states.
6.2.1
Normal State--State 1
This is the normal operating state for the processor.
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Features
6.2.2
AutoHALT Powerdown State--State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state. See the Intel(R) Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Power Down state, the processor will process bus snoops and interrupts.
Figure 6-1. Stop Clock State Machine
HALT Instruction and HALT Bus Cycle generated INIT#, BINIT#, INTR, NMI, SMI#, RESET#
2. Auto HALT Power Down State BCLK running. Snoops and interrupts allowed.
1. Normal State Normal execution.
STPCLK# Asserted Snoop Event Occurs Snoop Event Serviced STPCLK# Asserted STPCLK# De-asserted
STPCLK# De-asserted Snoop event occurs Snoop event serviced
4. HALT/Grant Snoop State BCLK running. Service snoops to caches.
3. Stop Grant State BCLK running. Snoops and interrupts allowed.
SLP# Asserted
SLP# De-asserted
5. Sleep State BCLK running. No snoops and interrupts allowed.
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Features
6.2.3
Stop-Grant State--State 3
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from the Stop-Grant state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should only be de-asserted one or more bus clocks after the de-assertion of SLP#. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the system bus (see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) will occur with the assertion of the SLP# signal. While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the system bus and it will latch interrupts delivered on the system bus. The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that it should return the processor to the Normal state.
6.2.4
HALT/Grant Snoop State--State 4
The processor will respond to snoop or interrupt transactions on the system bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop or interrupt transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or other agent on the system bus) or the interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.
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Features
6.2.5
Sleep State--State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can be entered only from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should be asserted only when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification, and may result in unapproved operation. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state and is held active as specified in the RESET# pin specification, the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure that the processor correctly executes the Reset sequence. Once in the Sleep state, the SLP# pin must be de-asserted if another asynchronous system bus event needs to occur. The SLP# pin has a minimum assertion of one BCLK period. When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.
6.3
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the Thermal Control Circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30-50%). Clocks often will not be off for more than 3.0 s when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/ inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may
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Intel(R) Pentium(R) 4 Processor on 0.13 Micron Process Datasheet
Features
cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines. The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor Control Register is written to a 1, the TCC will be activated immediately independent of the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control Register. In automatic mode, the duty cycle is fixed. However, in On-Demand mode, the duty cycle can be programmed from 12.5% on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used at the same time Automatic mode is enabled. However, if the system tries to enable the TCC via On-Demand mode at the same time automatic mode is enabled AND a high temperature condition exists, the duty cycle of the automatic mode will override the duty cycle selected by the On-Demand mode. An external signal, PROCHOT# (processor hot), is asserted when the processor detects that its temperature is at the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. The temperature at which the thermal control circuit activates is not user configurable and is not software visible. Besides the thermal sensor and TCC, the Thermal Monitor feature also includes one ACPI register, performance monitoring logic, bits in three model specific registers (MSR), and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Thermal Monitor feature. Thermal Monitor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. If automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling of the automatic or On-Demand modes, in the event of a catastrophic cooling failure the processor automatically shuts down when the silicon has reached a temperature of approximately 135 C. At this point the system bus signal THERMTRIP# goes active and stays active until RESET# has been initiated. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage (VCC) must be removed within 0.5 seconds.
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Features
6.3.1
Thermal Diode
The Pentium 4 processor on 0.13 micron process incorporates an on-die thermal diode. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. Table 6-2 and Table 6-3 provide the diode parameter and interface specifications. This thermal diode is separate from the Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Thermal Monitor.
Table 6-2. Thermal Diode Parameters
Symbol Parameter Min Typ Max Unit
A
Notes1
IFW n RT
Forward Bias Current Diode Ideality Factor Series Resistance
5 1.0011 1.0021 3.64
300 1.0030
1 2,3,4 2,3,4,5
NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized at 75 C. 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: IFW=Is *(e(qVD/nkT) -1) Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature. RT as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT*(N-1)*IFWmin]/[(nk/q)*ln N] Where Terror = sensor temperature error, N = sensor current ration, k = Boltzmann Constant, q = electronic charge.
Table 6-3. Thermal Diode Interface
Pin Name Pin Number Pin Description
THERMDA THERMDC
B3 C4
diode anode diode cathode
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Boxed Processor Specifications
Boxed Processor Specifications
7.1 Introduction
7
The Pentium 4 processor on 0.13 micron process will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from motherboards and standard components. The boxed Pentium 4 processor on 0.13 micron process will be supplied with a cooling solution. This chapter documents motherboard and system requirements for the cooling solution that will be supplied with the boxed Pentium 4 processor on 0.13 micron process This chapter is particularly important for OEMs that manufacture motherboards for system integrators. Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets]. Figure 7-1 shows a mechanical representation of a boxed Pentium 4 processor on 0.13 micron process. Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designer's responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platform and chassis. Refer to the Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines for further guidance.
Figure 7-1. Mechanical Representation of the Boxed Processor
NOTE: The airflow is into the center and out of the sides of the fan heatsink.
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Boxed Processor Specifications
7.2
7.2.1
Mechanical Specifications
Boxed Processor Cooling Solution Dimensions
This section describes the mechanical specifications of the boxed Pentium 4 processor on 0.13 micron process. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed Pentium 4 processor on 0.13 micron process. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 7-2 (Side Views), and Figure 7-3 (Top View). The airspace requirements for the boxed processor fan heatsink must also be incorporated into new motherboard and system designs. Airspace requirements are shown in Figure 7-6 and Figure 7-7. Note that some figures have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning.
Figure 7-2. Side View Space Requirements for the Boxed Processor
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Boxed Processor Specifications
Figure 7-3. Top View Space Requirements for the Boxed Processor
7.2.2
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines for details on the processor weight and heatsink requirements.
7.2.3
Boxed Processor Retention Mechanism and Heatsink Assembly
The boxed processor thermal solution requires a processor retention mechanism and a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket. The boxed processor will not ship with retention mechanisms but will ship with the heatsink attach clip assembly. Motherboards designed for use by system integrators should include the retention mechanism that supports the boxed Pentium 4 processor on 0.13 micron process. Motherboard documentation should include appropriate retention mechanism installation instructions. Note: The processor retention mechanism based on the Intel reference design should be used to ensure compatibility with the heatsink attach clip assembly and the boxed processor thermal solution. The heatsink attach clip assembly is latched to the retention tab features at each corner of the retention mechanism.
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Boxed Processor Specifications
The target load applied by the clips to the processor heat spreader for Intel's reference design is 75 15 lbf (maximum load is constrained by the package load capability). It is normal to observe a bow or bend in the board due to this compressive load on the processor package and the socket. The level of bow or bend depends on the motherboard material properties and component layout. Any additional board stiffening devices such as plates are not necessary and should not be used along with the reference mechanical components and boxed processor. Using such devices increase the compressive load on the processor package and socket, likely beyond the maximum load that is specified for those components. Refer to the Intel(R) Pentium(R) 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines for details on the Intel reference design.
7.3
7.3.1
Electrical Requirements
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the motherboard. The power cable connector and pinout are shown in Figure 7-4. Motherboards must provide a matched power header to support the boxed processor. Table 7-1 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal, which is an open-collector output that pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides VOH to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. Note: The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the boxed processor. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 7-5 shows the location of the fan power connector relative to the processor socket. The motherboard power header should be positioned within 4.33 inches from the center of the processor socket.
Figure 7-4. Boxed Processor Fan Heatsink Power Cable Connector Description
Pin 1 2 3
Signal GND +12V SENSE Straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pin pitch, 0.025" square pin width. Waldom*/Molex* P/N 22-01-3037 or equivalent. Match with straight pin, friction lock header on motherboard Waldom/Molex P/N 22-23-2031, AMP* P/N 640456-3, or equivalent.
123
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Boxed Processor Specifications
Table 7-1. Fan Heatsink Power and Signal Specifications
Description Min Typ Max Unit Notes
+12 V: 12 Volt fan power supply IC: Fan current draw SENSE: SENSE frequency
10.2
12
13.8 740
V mA pulses per fan revolution 1
2
NOTE: 1. Motherboard should pull this pin up to VCC with a resistor.
Figure 7-5. MotherBoard Power Header Placement Relative to Processor Socket
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Boxed Processor Specifications
7.4
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor.
7.4.1
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and is ultimately the responsibility of the system integrator. The processor temperature specification is found in Chapter 5. The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Table 5-1) in chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink be unimpeded. Airflow is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. Figure 7-6 and Figure 7-7 illustrate an acceptable airspace clearance for the fan heatsink. The air temperature entering the fan should be kept below 40 C. Again, meeting the processor's temperature specification is the responsibility of the system integrator.
Figure 7-6. Boxed Processor Fan Heatsink Airspace Keep-Out Requirements (Side 1 View)
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Boxed Processor Specifications
Figure 7-7. Boxed Processor Fan Heatsink Airspace Keep-Out Requirements (Side 2 View)
7.4.2
Variable Speed Fan
The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains below the lower set point. These set points, represented in Figure 7-8 and Table 7-2, can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis temperature should be kept below 38 C. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator.
Figure 7-8. Boxed Processor Fan Heatsink Set Points
Higher Set Point Highest Noise Level
Increasing Fan Speed & Noise
Lower Set Point Lowest Noise Level
X
Y
Z
Internal Chassis Temperature (Degrees C)
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Boxed Processor Specifications
Table 7-2. Boxed Processor Fan Heatsink Set Points
Boxed Processor Fan Heatsink Set Point (C) Boxed Processor Fan Speed Notes
Boxed Intel(R) Pentium(R) 4 Processors 2.80 GHz (and below)
X 33
When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds. Recommended maximum internal chassis temperature for worst-case operating environment. When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed.
1
Y = 40 Z 43
1
Boxed Intel(R) Pentium(R) 4 Processors 3 GHz (and above)
X 32
When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds. Recommended maximum internal chassis temperature for worst-case operating environment. When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed.
1
Y = 38 Z 40
NOTE:
1
1. Set point variance is approximately 1 C from fan heatsink to fan heatsink.
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Debug Tools Specifications
Debug Tools Specifications
8
Refer to the ITP 700 Debug Port Design Guide and the appropriate platform design guidelines for more detailed information regarding debug tools specifications (such as integration details).
8.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Pentium 4 processors on 0.13 micron process systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of the Pentium 4 processor on 0.13 micron process systems, the LAI is critical in providing the ability to probe and capture system bus signals. There are two sets of considerations to keep in mind when designing a Pentium 4 processor on 0.13 micron process system that can make use of an LAI: mechanical and electrical.
8.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI pins plug into the socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the Pentium 4 processor on 0.13 micron process heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.
8.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide.
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